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Paret, Paul (ORCID:0000000312660922)

Publications and source records attributed to Paret, Paul (ORCID:0000000312660922).

20 records · Page 2

Parametric Design Study of a Power Electronics Package

The lifetime of a power electronics package is, to a large extent, determined by the reliability of its bonded interfaces under major loading conditions in an operational environment. Based on the application-level requirements of the package, bonded interface material is selected based on the results obtained from accelerated tests such as thermal cycling and power cycling. In addition to evaluating the reliability through accelerated tests, it is important to consider the impact of other component layers on the thermomechanical performance of the interface material, both from a material and geometric perspective. The co-efficient of thermal expansion (CTE) mismatch introduced by the use of different materials within a package and its structural design plays a critical role in determining the interface material reliability. In this paper, we present the results of a parametric modeling study of a power electronics package under thermal cycling in which the materials and geometric design of the different component layers were varied with respect to a baseline design to understand their impact on the reliability of the interface material. We chose the volume-averaged strain energy density per cycle computed at the corner region of the interface material as the metric for the reliability comparisons. Our results indicate that in addition to the CTE mismatch, the stiffness of individual component layers has a major impact on reliability. Among the different baseplates that we studied, aluminum silicon-carbide baseplates offered superior reliability over their copper and aluminum counterparts. We also found that the magnitude of the impact of stiffness variation—amongst the adjacent layers—on the reliability of the solder joint is dependent on the inherent CTE mismatch between the layers.

47 OTHER INSTRUMENTATION↗

Power Electronics Materials and Bonded Interfaces - Reliability and Lifetime

The emergence of wide-bandgap (WBG) devices in power electronics packages has brought significant attention to the reliability and thermal performance of the bonded interfaces. These interfaces, such as die-attach and substrate-attach, need to withstand the severe stress induced on them by the high-temperature (> 200°C) operation of the WBG devices. Sintered silver and transient liquid phase alloys are key bonded interfaces that can enable the high-temperature operation of WBG devices, however it is essential to evaluate their reliability and study the possible failure mechanisms before they can be used in power electronics packages. Sintered silver is already being adopted in commercial packages as a die-attach, but large-area substrate-attach offers additional reliability challenges. In this project, we investigate the reliability of these interface materials under accelerated thermal cycling and correlate these results with finite element simulations to develop lifetime prediction models. The failure mechanisms of these bonded interfaces are also studied.

47 OTHER INSTRUMENTATION↗