Engineering topics
Park, Ji-Hoon
Publications and source records attributed to Park, Ji-Hoon.
Revealing Variable Dependences in Hexagonal Boron Nitride Synthesis via Machine Learning
Wafer-scale monolayer two-dimensional (2D) materials have been realized by epitaxial chemical vapor deposition (CVD) in recent years. To scale up the synthesis of 2D materials, a systematic analysis of how the growth dynamics depend on the growth parameters is essential to unravel its mechanisms. However, the studies of CVD-grown 2D materials mostly adopted the control variate method and considered each parameter as an independent variable, which is not comprehensive for 2D materials growth optimization. Herein, we synthesized a representative 2D material, monolayer hexagonal boron nitride (hBN), on single-crystalline Cu (111) by epitaxial chemical vapor deposition and varied the growth parameters to regulate the hBN domain sizes. Furthermore, we explored the correlation between two growth parameters and provided the growth windows for large flake sizes by the Gaussian process. Here, this new analysis approach based on machine learning provides a more comprehensive understanding of the growth mechanism for 2D materials.
Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform
Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2 V -1 s -1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.