Engineering topics

Prinzie, J.

Publications and source records attributed to Prinzie, J..

3 records

DOE OSTI2026

Design and Testing of the Endcap Concentrator ASICs for the CMS High-Granularity Calorimeter Upgrade

A major upgrade of the High-Granularity Calorimeter (HGCAL) in the CMS detector is planned for Long-Shutdown 3 (LS3), currently expected to start in 2026. This upgrade will contain over 6 million channels and the electronics will be required to be low power and to withstand a radiation environment with a High-Energy Hadron flux of 3x10**6 particles per square centimeter per second. The solution to this significant challenge is the two Endcap Concentrator (ECON) ASICs, ECON-T and ECON-D, working in tandem with the HGCROC front-end ASIC. The two ECON ASICs provide critical on-detector data reduction for both the 40 MHz trigger path (ECON-T) and 750 kHz data acquisition path (ECON-D) of the HGCAL. The ASICs are fabricated in 65nm CMOS. They are rad-tolerant to 600 Mrad with low power consumption (<2.5 mW/channel). This presentation will be a comprehensive description of each ECON design, including the infrastructure that they share as well as the elements that make each unique. The presentation will also include functionality and radiation tests for both ASICs, and the first high statistics characterization results from the full production of 75k ECON-D and ECON-T ASICs.

Hoff, James R. [Fermilab] (ORCID:0000000163514592)↗

DOE OSTI2022

A radiation tolerant clock generator for the CMS endcap timing layer readout chip

Here, we present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm 2 /mg.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗