Cost models and economical packaging of LSI's
Report discusses mathematical models used to estimate costs of developing and fabricating microcircuits. Second part discusses LSI packaging using tape chip carrier technology.
Himmel, R. P.↗
Engineering topics
Rothrock, C. W.
Publications and source records attributed to Rothrock, C. W..
Design, processing and testing of LSI arrays, hybrid microelectronics task
Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.
Himmel, R. P.↗