Engineering topics

Seaton, Chad

Publications and source records attributed to Seaton, Chad.

3 records

DOE OSTI2018

Commissioning of JLab Vertical Cavity Processing System for SRF Nb Single Cell and Multicell Cavity With HF-Free Pulse-Reverse Electopolishing

Pulse reversed electropolishing of niobium SRF cavities, using a dilute aqueous H2SO4 electrolyte without HF yields equivalent RF performance with traditional EP. Comparing with present EP process for Nb SRF cavity which uses 1:10 volume ratio of HF (49%) and H2SO4 (98%), pulse reverse EP (also known as bipolar EP (BPEP)) is ecologically friendly and uses relatively benign electrolyte options for cavity processing. In this study, we report the commissioning of a new vertical cavity processing system for SRF Nb single cell and multi-cell cavities with HF-free pulse-reverse electropolishing at Jefferson Lab, together with RF test of cavities being processed. We report the scale-up challenges and interpretations from process R&D to implementation.

Tian, Hui↗

DOE OSTI2018

NEW EPICS/RTEMS IOC BASED ON ALTERA SOC AT JEFFERSON LAB

A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA is being designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 Hard Processor System (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via U-Boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDR3 SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications at runtime. U-Boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run RTEMS and EPICS. The first design of the SoC IOC will be compatible with Jefferson Lab’s current PC104 IOCs, which have been running in CEBAF 10 years. The next design would be mounting in a chassis and connected to a daughter card via standard HSMC connectors. This standard SoC IOC will become the next generation of low-level IOC for the accelerator controls at Jefferson Lab.

Yan, Jianxun↗

DOE OSTI2018

MODBUS APPLICATION AT JEFFERSON LAB

Modbus is a client/server communication model. In our applications, the embedded Ethernet device XPort is designed as the server and a SoftIOC running EPICS Modbus is the client. The SoftIOC builds a Modbus request from parameter contained in a demand that is sent by the EPICS application to the Modbus Client interface. On reception of the Modbus request, the Modbus server activates a local action to read, write, or achieve some other action. So, the main Modbus server functions are to wait for a Modbus request on 502 TCP port, treat this request, and then build a Modbus response.

Yan, Jianxun↗