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Shah, Biren N.

Publications and source records attributed to Shah, Biren N..

The ISARA Mission – Flight Demonstration of a High Gain Ka-Band Antenna for 100Mbps Telecom

The NASA sponsored ISARA (Integrated Solar Array and Reflectarray Antenna) mission successfully demonstrated a 100 Mbps Ka-band CubeSat communications capability. The enabling technology is a high gain reflectarray antenna integrated into a modified Pumpkin “Turkey Tail” solar array which wraps around the spacecraft body, essentially requiring near zero volume to accommodate. A simple low gain feed is used to distribute RF power to the reflectarray through free space. The 0.5kg ISARA antenna mass is compatible with the requirements of a 3U (10x10x10 cm3) spacecraft. The ISARA mission validated this approach in a flight technology demonstration. A unique on-orbit measurement system provided accurate measurement of the antenna gain from space. This system demonstrated 100Mbps downlink data rate capability using a relatively simple ground station with a 70cm parabolic reflector antenna. The spacecraft also verified ISARA solar panel output power and demonstrated the operational capability to accurately point the antenna to a Ka-band ground station, a key requirement for a telecom system. ISARA achieved a number of technological firsts. It is believed to be the first reflectarray antenna flown in space, first high gain antenna integrated with solar panels, first calibrated reflectarray antenna gain and pattern measurement performed from space and the first 3U CubeSat to demonstrate 100 Mbps using a small, low-cost ground station.

Martin, Jerami M.

High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors

Exponential growth in microelectronics technology such as field-programmable gate arrays (FPGAs) has enabled high-performance spaceborne instruments with increasing onboard data processing capabilities. As a commonly used digital signal processing (DSP) building block, fast Fourier transform (FFT) has been of great interest in onboard data processing applications, which needs to strike a reasonable balance between high-performance (throughput, block size, etc.) and low resource usage (power, silicon footprint, etc.). It is also desirable to be designed so that a single design can be reused and adapted into instruments with different requirements. The Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture was developed, in which the high-throughput benefits of the parallel FFT structure and the low resource usage of Singleton s single butterfly method is exploited. The result is a wide-kernel, multipass, adaptive FFT architecture. The 32K-point MPWK-FFT architecture includes 32 radix-2 butterflies, 64 FIFOs to store the real inputs, 64 FIFOs to store the imaginary inputs, complex twiddle factor storage, and FIFO logic to route the outputs to the correct FIFO. The inputs are stored in sequential fashion into the FIFOs, and the outputs of each butterfly are sequentially written first into the even FIFO, then the odd FIFO. Because of the order of the outputs written into the FIFOs, the depth of the even FIFOs, which are 768 each, are 1.5 times larger than the odd FIFOs, which are 512 each. The total memory needed for data storage, assuming that each sample is 36 bits, is 2.95 Mbits. The twiddle factors are stored in internal ROM inside the FPGA for fast access time. The total memory size to store the twiddle factors is 589.9Kbits. This FFT structure combines the benefits of high throughput from the parallel FFT kernels and low resource usage from the multi-pass FFT kernels with desired adaptability. Space instrument missions that need onboard FFT capabilities such as the proposed DESDynl, SWOT (Surface Water Ocean Topography), and Europa sounding radar missions would greatly benefit from this technology with significant reductions in non-recurring cost and risk.

NguyenKobayashi, Kayla

Adaptation of the Electra Radio to Support Multiple Receive Channels

Proposed future Mars missions plan communication between multiple assets (rovers). This paper presents the results of a study carried out to assess the potential adaptation of the Electra radio to a multi-channel transceiver. The basic concept is a Frequency Division multiplexing (FDM) communications scheme wherein different receiver architectures are examined. Options considered include: (1) multiple IF slices, A/D and FPGAs each programmed with an Electra baseband modem; (2) common IF but multiple A/Ds and FPGAs and (3) common IF, single A/D and single or multiple FPGAs programmed to accommodate the FDM signals. These options represent the usual tradeoff between analog and digital complexity. Given the space application, a common IF is preferable; however, multiple users present dynamic range challenges (e.g., near-far constraints) that would favor multiple IF slices (Option 1). Vice versa, with a common IF and multiple A/Ds (Option 2), individual AGC control of the A/Ds would be an important consideration. Option 3 would require a common AGC control strategy and would entail multiple digital down conversion paths within the FPGA. In this paper, both FDM parameters as well as the different Electra design options will be examined. In particular, signal channel spacing as a function of user data rates and transmit powers will be evaluated. In addition, tradeoffs between the different Electra design options will be presented with the ultimate goal of defining an augmented Electra radio architecture for potential future missions.

Time Division multiplexing

Symbol lock detection implemented with nonoverlapping integration intervals

A symbol lock detector is introduced for an incoming coherent digital communication signal which utilizes a subcarrier modulated with binary symbol data, d(sub k), and known symbol interval T by integrating binary values of the signal over nonoverlapping first and second intervals selected to be T/2, delaying the first integral an interval T/2, and either summing or multiplying the second integral with the first one that preceded it to form a value X(sub k). That value is then averaged over a number M of symbol intervals to produce a static value Y. A symbol lock decision can then be made when the static value Y exceeds a threshold level delta.

Shihabi, Mazen M.

Parallel Digital Phase-Locked Loops

Wide-band microwave receivers of proposed type include digital phase-locked loops in which band-pass filtering and down-conversion of input signals implemented by banks of multirate digital filters operating in parallel. Called "parallel digital phase-locked loops" to distinguish them from other digital phase-locked loops. Systems conceived as cost-effective solution to problem of filtering signals at high sampling rates needed to accommodate wide input frequency bands. Each of M filters process 1/M of spectrum of signal.

Sadr, Ramin

Comparison Of Four FFT-Based Frequency-Acquisition Techniques

Report presents comparative theoretical analysis of four conceptual techniques for initial estimation of carrier frequency of suppressed-carrier, binary-phase-shift-keyed radio signal. Each technique effected by open-loop analog/digital signal-processing subsystem part of Costas-loop phase-error detector functioning in closed-loop manner overall.

Shah, Biren N.

Three Alternative Symbol-Lock Detectors

Three symbol-lock detectors proposed as alternatives in advanced receivers processing non-return-to-zero binary data signals. Two perform operations similar to those of older square-law and absolute-value types. However, integrals computed during nonoverlapping symbol periods and, therefore, only one integrator needed in each such detector. Proposed detectors simpler, but performances worse because noises in overlapping samples correlated, whereas noises in nonoverlapping samples not correlated. Third detector is signal-power-estimator type. Signal integrated during successive half symbol cycles, and therefore only one integrator needed. Half-cycle integrals multiplied to eliminate effect of symbol polarity, and products accumulated during M-cycle observation period to smooth out estimate of signal power. If estimated signal power exceeds threshold, delta, then lock declared.

Shihabi, Mazen M.

Performance Of The Split-Symbol Moments Estimator

Report presents analysis of performance of Split-Symbol Moments Estimator (SSME) algorithm. Designed to estimate symbol signal-to-noise ratio of radio signal modulated by binary data pulses of period T and received in presence of additive white Gaussian noise. Incoming signal and noise first filtered, then sampled Ns - T/Ts times per symbol period. This study focuses on performance of SSME in case in which frequency width limited by digital filter and inter-symbol interference is thereby generated.

Shah, Biren N.

Open-Loop Acquisition Of Frequency In BPSK

Proposed open-loop analog/digital signal-processing system would be Costas-loop error detector functioning in closed-loop manner overall. Detector estimates difference between frequency of input signal and internal reference oscillator. Estimate used to close frequency-control loop. Precise symbol timing not necessary. Performance better than systems that effect open-loop acquisition using integrators instead of low-pass filters in arms of Costas loops and in which performance varies with symbol timing.

Shah, Biren N.

Open-Loop Acquisition Of Suppressed Carrier Signals

Three digital techniques for open-loop acquisition of suppressed carrier signals in presence of binary-phase-shift-keyed (BPSK) modulation representing non-return-to-zero (NRZ) data symbols. Based on assumption that offset, tau, between timing of symbols and clock in receiver unknown, but fixed fraction of symbol period, T. In all three, fast Fourier transforms (FFT's) performed on outputs of integrate-and-dump filters that are parts of Costas-type loops used to demodulate BPSK signals. Timing of integrate-and-dump filters constant. Outputs mixed to obtain an error signal.

Shah, Biren N.

Acquisition Performances Of QPSK Carrier-Tracking Loops

Report presents comparative study of acquisition performances of several types of carrier-signal-tracking loops for reception of quadrature phase-shift keying (QPSK) signals. Loops classified into three types: maximum a-posteriori, (MAP) estimation loop, Costas cross-over loop, and generalized Costas loop. Mathematical models developed. In-phase and quadrature signals generated numerically and processed according to loop algorithms. Results show though MAP loop produces smallest squaring loss at all signal-to-noise ratios, others sometimes exhibit shorter acquisition time and greater probability of acquisition.

Hinedi, Sami M.

Real-time edge-enhanced optical correlator

The performance of five symbol lock detectors are compared. They are the square-law detector with overlapping (SQOD) and non-overlapping (SQNOD) integrators, the absolute value detectors with overlapping and non-overlapping (AVNOD) integrators and the signal power estimator detector (SPED). The analysis considers various scenarios when the observation interval is much larger or equal to the symbol synchronizer loop bandwidth, which has not been considered in previous analyses. Also, the case of threshold setting in the absence of signal is considered. It is shown that the SQOD outperforms all others when the threshold is set in the presence of signal, independent of the relationship between loop bandwidth and observation period. On the other hand, the SPED outperforms all others when the threshold is set in the presence of noise only.

Shihabi, Mazen M.