Cost models and economical packaging of LSI's
Report discusses mathematical models used to estimate costs of developing and fabricating microcircuits. Second part discusses LSI packaging using tape chip carrier technology.
Himmel, R. P.↗
Engineering topics
Stuhlbarg, S. M.
Publications and source records attributed to Stuhlbarg, S. M..
Cost savings in LSI fabrication
One year study program was divided into three tasks: to identify costs factors involved in packaged electronic subsystems as function of LSI density and reliability; to select most promising factors that might be modified to reduce costs in high-density packaging; and to investigate cost-saving beam tape technology for producing high-volume discrete-device packages. Results are published in 67 page report.
Himmel, R. P.↗
Design, processing and testing of LSI arrays, hybrid microelectronics task
Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.
Himmel, R. P.↗
Design, processing and testing of LSI arrays: Hybrid microelectronics task
Mathematical cost factors were generated for both hybrid microcircuit and printed wiring board packaging methods. A mathematical cost model was created for analysis of microcircuit fabrication costs. The costing factors were refined and reduced to formulae for computerization. Efficient methods were investigated for low cost packaging of LSI devices as a function of density and reliability. Technical problem areas such as wafer bumping, inner/outer leading bonding, testing on tape, and tape processing, were investigated.
Himmel, R. P.↗
Design, processing and testing of LSI arrays hybrid microelectronics task
Those factors affecting the cost of electronic subsystems utilizing LSI microcircuits were determined and the most efficient methods for low cost packaging of LSI devices as a function of density and reliability were developed.
Himmel, R. P.↗