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Sundaram, Mani

Publications and source records attributed to Sundaram, Mani.

5 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Long-Wavelength 640 x 486 GaAs/AlGaAs Quantum Well Infrared Photodetector Snap-Shot Camera

A 9-micrometer cutoff 640 x 486 snap-shot quantum well infrared photodetector (QWIP) camera has been demonstrated. The performance of this QWIP camera is reported including indoor and outdoor imaging. The noise equivalent differential temperature (NE.deltaT) of 36 mK has been achieved at 300 K background with f/2 optics. This is in good agreement with expected focal plane array sensitivity due to the practical limitations on charge handling capacity of the multiplexer, read noise, bias voltage, and operating temperature.

Gunapala, Sarath D.↗
NASA NTRS1996

Sharp Infrared Eyes The Journey of QWIPs from Concept to Large Inexpensive Sensitive Arrays in Hand-held Infrared Cameras

One of the simplest device realizations of the classic particle-in-a-box problem of basic quantum mechanics is the Quantum Well Infrared Photodetector (QWIP). Optimization of the detector design and material growth and processing has culminated in the realization of a camera with a large (256x256 pixel) focal plane array of QWIPs which can see at 8.5 mu m, holding forth great promise for a variety of applications in the 6-25 mu m wavelength range.

Quantum Well Infrared Photodetector QWIP quantum m↗
NASA NTRS1992

A 600-MHz median-type digital filter on GaAs

A single-chip GaAs implementation of an FIR-median hybrid filter is presented. The very high-speed digital filter combines linear averaging structures to a median selector. The filter operates on 5-b samples with ECL-compatible I/O interfaces. The 1500-transistor LSI device with 3.6-sq mm chip size was processed with a 1.0-micron GaAs depletion-mode (D-mode) MESFET process. The filter demonstrates 600-MHz sample rate when operated in test mode utilizing special built-in feedback.

Vainjo, Olli↗
NASA NTRS1988

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Long, Stephen I.↗