Engineering topics

Tran, M.

Publications and source records attributed to Tran, M..

4 records

NASA NTRS1995

Low Temperature Performance of High-Speed Neural Network Circuits

Artificial neural networks, derived from their biological counterparts, offer a new and enabling computing paradigm specially suitable for such tasks as image and signal processing with feature classification/object recognition, global optimization, and adaptive control. When implemented in fully parallel electronic hardware, it offers orders of magnitude speed advantage. Basic building blocks of the new architecture are the processing elements called neurons implemented as nonlinear operational amplifiers with sigmoidal transfer function, interconnected through weighted connections called synapses implemented using circuitry for weight storage and multiply functions either in an analog, digital, or hybrid scheme.

artificial neural networks image processing signal↗

NASA NTRS1994

Low Power Analog Neurosynapse Chips for a 3-D 'Sugarcube' Neuroprocessor

Object discrimination and patttern recognition are computationally intensive and for many defense and commercial applications, speed is of the essence.

3-D VLSI architecture reconfigurable multilayer pe↗

NASA NTRS1994

Wideband bandpass filters employing broadside-coupled microstrip lines for MIC and MMIC applications

Wideband bandpass filters employing half-wavelength broadside-coupled microstrip lines suitable for microwave and mm-wave integrated monolithic integrated circuits (MIC and MMIC) are presented. Several filters have been developed at X-band (8 to 12 GHz) with 1 dB insertion loss. Fair agreement between the measured and calculated results has been observed. The analysis of the broadside-coupled microstrip lines used in the filters, based on the quasi-static spectral domain technique, is also described.

Tran, M.↗

NASA NTRS1992

Learning and optimization with cascaded VLSI neural network building-block chips

To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

Duong, T.↗