Search NASA⌕ Search

Engineering topics

Trippe, James

Publications and source records attributed to Trippe, James.

8 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

The Effects of Threshold Voltage and Number of Fins per Transistor on the TID Response of GF 12LP Technology

This abstract presents a comprehensive analysis of total ionizing dose (TID) response in GlobalFoundries’ 12LP 12nm bulk FinFET technology using 10keV X-rays. Devices with higher threshold voltages (VTs) demonstrated lower increases in off-state leakage current (IDS,OFF) post-irradiation, highlighting the mitigating role of high VT in TID response. Our data shows that transistors with fewer fins exhibit superior TID resistance, implying lower susceptibility to radiation effects. Our study also probed two bias conditions, "Gate-On" and "Pass-Gate," with the former displaying more severe TID degradation. Interestingly, p-type devices displayed negligible degradation, underscoring their inherent resilience to TID effects. Additionally, medium thick n-type devices echoed the fin-count-dependent TID response observed in other transistor types, further strengthening our findings. These results underscore the importance of strategic transistor selection and design for enhancing the TID resilience of future CMOS FinFET architectures, particularly critical in radiation-intense environments.

42 ENGINEERING↗
DOE OSTI2021

Impact of Surface Recombination on Single-Event Charge Collection in an SOI Technology

Semiconductor–insulator interfaces play an important role in the reliability of integrated devices; however, the impact of these interfaces on the physical mechanisms related to single-event effects has not been previously reported. We present experimental data that demonstrate that single-event charge collection can be impacted by changes in interface quality. The experimental data, combined with simulations, show that single-event response may depend on surface recombination at interface defects. The effect depends on strike location and increases with increasing linear energy transfer (LET). Surface recombination can affect single-event charge collection for interfaces with a surface recombination velocity (SRV) of 1000 cm/s and is a dominant charge collection mechanism with SRV >10 5 cm/s.

42 ENGINEERING↗
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗