Engineering topics

Tyree, V. C.

Publications and source records attributed to Tyree, V. C..

6 records

NASA NTRS1981

Real-time multiple-look synthetic aperture radar processor for spacecraft applications

A spaceborne synthetic aperture radar (SAR) having pipeline multiple-look data processing is described which makes use of excessive azimuth bandwidth in radar echo signals to produce multiple-looking images. Time multiplexed single-look image lines from an azimuth correlator go through an energy analyzer which analyzes the mean energy in each separate look to determine the radar antenna electric boresight for use in generating the correct reference functions for the production of high quality SAR images. The multiplexed single look image lines also go through a registration delay to produce multi-look images.

Wu, C.↗

NASA NTRS1980

Azimuth correlator design for IC chip

Azimuth correlator circuit synthetic-aperature radar (SAR) is designed for single integrated circuit (IC) chip. Azimuth correlator modules constructed with sets of such chips could make real-time signal processing possible. Primary advantages are realized in areas of weight and power requirement reductions.

Tyree, V. C.↗

NASA NTRS1978

Simplified data compressor

Image data are compressed for transmission by simple, economical circuitry. Compressor handles data in blocks of 64 samples. Mean from previous line is subtracted, and pseudo-random sequence of positive and negative 1's multiplies samples of each block. Hadamard transform applied to blocks yields 64 transform coefficients. Each coefficient is compared with approximation to corresponding coefficient of previous line, and difference is quantized. Values are transmitted or stored. Procedure is reversed to reproduce image.

Rice, R. F.↗

NASA NTRS1978

Custom large scale integrated circuits for spaceborne SAR processors

The application of modern LSI technology to the development of a time-domain azimuth correlator for SAR processing is discussed. General design requirements for azimuth correlators for missions such as SEASAT-A, Venus orbital imaging radar (VOIR), and shuttle imaging radar (SIR) are summarized. Several azimuth correlator architectures that are suitable for implementation using custom LSI devices are described. Technical factors pertaining to selection of appropriate LSI technologies are discussed, and the maturity of alternative technologies for spacecraft applications are reported in the context of expected space mission launch dates. The preliminary design of a custom LSI time-domain azimuth correlator device (ACD) being developed for use in future SAR processors is detailed.

Tyree, V. C.↗

NASA NTRS1978

Custom large scale integrated circuits for spaceborne SAR processors

The application of modern LSI technology to the development of a time-domain azimuth correlator for SAR processing is discussed. General design requirements for azimuth correlators for such missions as Seasat-A, Venus Orbital Imaging Radar, and Shuttle Imaging Radar are summarized. Several azimuth correlator architectures suitable for implementation using custom LSI devices are described. Technical factors pertaining to selection of appropriate LSI technologies are discussed, and the maturity of alternative technologies for spacecraft application is examined in the context of the expected launch dates. In particular, it is demonstrated that a custom LSI device is practical for a system as complex as the DMSP.

Tyree, V. C.↗

NASA NTRS1976

The unified data system - A distributed processing network for control and data handling on a spacecraft

This paper presents the results obtained in a continuing investigation of real-time distributed processing systems which is being conducted at the Jet Propulsion Laboratory. A distributed processor architecture has been developed for control and data handling on a planetary spacecraft. This system, designated the Unified Data System, has been implemented in a feasibility breadboard. The following aspects of the Unified Data System are described: (1) standardized building block elements and their configuration into microprocessor modules, (2) a highly redundant bus structure which connects the various modules and facilitates intercommunications with minimal software support, (3) the structure of software within the individual modules and its coordination between modules, and (4) the mechanisms by which fault-tolerance can be implemented within the network. Through the attributes of multilevel standardization, simplicity, and flexibility, this system is expected to result in significant cost savings to future spacecraft missions.

Rennels, D. A.↗