Engineering topics

Van Rosendale, J.

Publications and source records attributed to Van Rosendale, J..

3 records

NASA NTRS1986

On the structure of parallelism in a highly concurrent PDE solver

A parallel multigrid algorithm for solving elliptic partial differential equations is developed and evaluated. A V-cycle multigrid method is altered to increase the degree of parallelism. A numerical analysis of the resulting concurrent-iteration multigrid algorithm is performed; its architectural implications are considered; highly parallel systems without shared memory are examined (including mesh-connected arrays, mesh-shuffle-connected systems, permutation networks, and direct VLSI embeddings); and the results of numerical experiments are presented in tables and graphs.

Gannon, D.↗

NASA NTRS1984

On the impact of communication complexity on the design of parallel numerical algorithms

This paper describes two models of the cost of data movement in parallel numerical alorithms. One model is a generalization of an approach due to Hockney, and is suitable for shared memory multiprocessors where each processor has vector capabilities. The other model is applicable to highly parallel nonshared memory MIMD systems. In this second model, algorithm performance is characterized in terms of the communication network design. Techniques used in VLSI complexity theory are also brought in, and algorithm-independent upper bounds on system performance are derived for several problems that are important to scientific computation.

Gannon, D. B.↗

NASA NTRS1983

Programming substructure computations for elliptic problems on the CHiP system

A number of studies have been conducted with the aim to apply parallel computation to problems associated with solving finite element equations arising in structural mechanics and fluid dynamics. These studies have provided many important results. The present investigation is concerned with a set of experiments designed to test two ideas, including configurability and substructuring. The considered algorithms and tests are intended for implementation on the Configurable, Highly Parallel (CHiP) family of architecture described by Snyder (1982). The ChiP computer is composed of homogeneous processing elements (PEs) placed at regular intervals in a lattice of programmable switches. Two examples of the role of configurability and substructuring for simple iterative algorithms are considered, giving attention to conjugate gradient iterations, and tridiagonal systems of equations.

Gannon, D.↗