Hardware Design of a 13.8-kV/3-MVA PV Plus Storage Solid-State Transformer (PVS-SST)
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Engineering topics
Publications and source records attributed to Vetrivelan, Adithyan.
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This paper presents a loss-optimized Triple Phase-Shift (TPS) switching strategy for Dual-Active Bridge (DAB) based converters. The proposed strategy considers minimizing total converter loss with respect to minimizing device rms cur-rents, enabling Zero-Voltage Switching (ZVS) turn-on of devices and accurate control of device turn-off current. A model for switching currents is presented, followed by a loss model and optimization strategy. A 1.3kV/100kW prototype based on SiC MOSFETs was used in this work and experimental results up to 10kW show the proposed TPS strategy to be more efficient for operation.
Silicon-carbide based, multi-level converters with dual-active-bridge (DAB) are getting attention for medium voltage, direct grid-connected, utility-scale photovoltaic (PV) applications due to their higher efficiency and power density. To de-risk complex control development for these high-voltage and high-power inverters, hardware-in-the-loop techniques are often required. Due to the high switching frequency and the large number of power electronic switches, off-the-shelf, real-time simulation tools are not yet fully developed for this application, even with FPGA-based simulators. To address this, a new co-simulation approach in FPGA is presented that utilizes Time-Stamped Bridge (TSB) for the higher frequency converters along with detailed fixed conductance based discrete device simulation of the rest of the circuit. A complex DAB-based PV converter with maximum switching frequency of 50 kHz is successfully simulated in real-time in the FPGA and the results are compared with offline simulation results. A controller hardware-in-the-loop (CHIL) platform is developed to demonstrate real-time, closed-loop test results for this DAB-based PV converter.
This paper presents a lossless regenerative dV/dt snubber circuit for PWM converters to achieve high-efficiency high power-density without significant cost and reliability penalties. The dV/dt snubber employs lossless capacitors for each MOSFET device in a converter to provide an additional path to store the switching energy during turn-off transient and decrease the actual turn-off loss of the MOSFET channel. A novel mathematical turn-off loss model is built to separate the actual turn-off loss of the MOSFET channel and the recycling switching energy stored in the total equivalent output capacitance including Coss, the dV/dt snubber, and etc. Necessary snubber optimization strategy is proposed in order to balance the turn-off loss with ZVS operation range and deadtime conduction loss, and thereby achieving an optimal efficiency performance. To prove the validity and accuracy of the novel turn-off loss model and optimization strategy, the dV/dt snubber has been incorporated into a 1.3kV/200kW DC/DC and a 1kV/70kVA DC/AC PWM converters. Experimental results are given to demonstrate the validity of the proposed dV/dt snubber capacitors and optimization strategy.