Engineering topics
Publications and source records attributed to Wallis, D. E..
Queuing strategy for communications along shared data bus minimizes number of data lines while always assuring user of highest priority given access to bus. New system handles up to 32 user demands on 17 data lines that previously serviced only 17 demands.
Unit delivers blocks of quadrature data to computer memory. Contains 105 integrated circuit packages in 19 by 3 1/2 inch (48.26 by 8.39 cm) rack mounted drawer with internal force air blower. Intended for synchronous sampling of quadrature pairs of data, samples with minimal skew (about 10 nanoseconds) using video-type high-speed sampling technology. Unit equipped for computer controlled self-testing. Originally developed for planetary radar data-acquisition system.
Accurate vehicle position determination over 50 by 50-km service area accomplished by low-frequency-radio navigational system comprised of four frequency/phase comparison transmitters and receivers. Use of grid-calibration table permits accurate position determination in vehicle receiver system.
A method of continuous wave navigation using four transmitters operating at sufficiently low frequencies to assure essentially pure groundwave operation is described. The transmitters are keyed to transmit constant bursts (1/4 sec) in a time-multiplexed pattern with phase modulation of at least one transmitter for identification of the transmitters and with the ability to identify the absolute phase of the modulated transmitter and the ability to modulate low rate data for transmission. The transmitters are optimally positioned to provide groundwave coverage over a service region of about 50 by 50 km for the frequencies selected in the range of 200 to 500 kHz, but their locations are not critical because of the beneficial effect of overdetermination of position of a receiver made possible by the fourth transmitter. Four frequencies are used, at least two of which are selected to provide optimal resolution. All transmitters are synchronized to an average phase as received by a monitor receiver.
Transverse mercator projection, surface of Earth or other spheroid is mapped onto cylinder tangent at meridian of longitude. New method performs mapping by means of mathematical series in which higher order terms correct for deviation from exact sphericity. New method yields precise geodetic maps.
Field programmable logic array (FPLA) is used to make 3-bit arithmetic logic unit (ALU) for large integrator that can be read and cleared while new data is added to begin new integral. Arrangement of device can provide for full carry/lookahead capability with minimum gate delays.
The Jet Propulsion Laboratory is engaged in the early phases of conceptual, preliminary design, and feasibility demonstration studies leading to determination of a design and implementation of the Army's proposed Mobile Automated Field Instrumentation System (MAFIS). An overview is provided of the current design concept for an experimental radio navigation subsystem to be implemented in the field as a part of the MAFIS study effort. Objectives of MAFIS include mobility, field-ruggedness and longevity of equipment, and low acquisition and life-cycle costs. The navigation subsystem comprises a 4-station radio transmitter network, plus the navigation receivers, network monitoring receivers and communications links, and interface to the command/control 'central' for transmitter status monitoring. Attention is given to accuracy goals, radio propagation effects, transmitter arrangement, radio-frequency allocations, position initialization and lane resolution, and transmitter and receiver functions.
Some codes for arbitration of priorities among subsystem computers or peripheral device controllers connected to a parallel data bus are described. At arbitration time, several subsystems present wire-OR, parallel code words to the bus, and the central computer can identify the subsystem of highest priority and determine which of two or more transmission services the subsystem requires. A mathematical discussion of the optimality of the codes with regard to the number of subsystems that may participate in the scheme for a given number of wires is presented along with the number of services that each subsystem may request.
A 4-bit and a 3-bit adder are described which can be implemented under special hardware restrictions. The chip to be used is field-programmable logic array (FPLA) with 12 input lines, 50 AND gates inside, and output through only 6 OR gates. The context in which it is being used requires an enable function which can suppress one of the two numbers to be added. The 3-bit enabled adder is compatible with lookahead-carry mechanizations using the 74S182.