Search NASASearch

Engineering topics

Wang, J. J.

Publications and source records attributed to Wang, J. J..

Electrostatic Precipitation for Cleaning Mars Atmospheric ISRU Intakes

Future Mars ISRU atmospheric intakes are estimated to ingest several hundred grams of dust over their lifetime. The Electrostatics and Surface Physics Laboratory at NASA's Kennedy Space Center is developing a dust removal system based on a mature terrestrial technology - electrostatic precipitation. In this technology, a high voltage and grounded collection electrode create a corona discharge which charges particles in a dust-laden flow. The resulting electric field between the high voltage and collection electrodes drive the charged particles toward the collection electrode. This paper presents the design of the electrostatic precipitator and preliminary results.

Precipitator

An overview of results from the ion diagnostics sensors flown on DS1

The Deep Space 1 (DS1) mission has successfully validated the use of ion propulsion technology for interplanetary spacecraft. The NASA Solar Electric Propulsion (SEP) Technology Applications Readiness (NSTAR) Project developed the Ion Propulsion Subsystem (IPS) for DS1. As part of the NSTAR validation effort, the NSTAR Project included a diagnostics element to characterize the local environment produced during IPS operations and its effects on spacecraft subsystems and science instruments. An integrated, comprehensive set of diagnostics, the NSTAR Diagnostics Package (NPD) was developed and operated on DS1 to characterize the IPS environment. The DS1 Spacecraft Team officially assigned the name “IPS Diagnostics Subsystems (IDS)” to the NDP for the DS1 mission. During the technology validation phase of the DS1 mission, a large amount of data was collected from the IDS under a variety of IPS operating conditions. IDS was able to characterize the contamination environment, charge-exchange xenon ion and electron population and energies, plasma noise and electromagnetic noise, and magnetic fields associated with IPS. The results presented here describe the charge-exchange plasma, contamination, plasma wave/EMI, and DC magnetic environments critical to designers of future space missions using ion propulsion

Henty, M. D.

A SEU-Hard Flip-Flop for Antifuse FPGAs

A single event upset (SEU)-hardened flip-flop has been designed and developed for antifuse Field Programmable Gate Array (FPGA) application. Design and application issues, testability, test methods, simulation, and results are discussed.

Katz, R.

New Instrumentation, Patterns and Their Effects on TID Testing of Antifuse-Based FPGAs

TID-induced leakage currents for some families of antifuse-based Field Programmable Gate Array (FPGA) devices are significantly affected by the state of bias of a device's internal nodes; proper consideration of this effect is essential for proper testing of these devices and interpretation of test results. Variations in TID performance based on utilization of different internal logic modules for implementing identical circuits may be utilized by circuit designers for improvement in TID performance by tailoring the placement algorithm. Propagation delays are significantly affected by TID-induced damage for the devices of 54SX32S family.

Kleyner, Igor

Validated Feasibility Study of Integrally Stiffened Metallic Fuselage Panels for Reducing Manufacturing Costs

The continual need to reduce airframe cost and the emergence of high speed machining and other manufacturing technologies has brought about a renewed interest in large-scale integral structures for aircraft applications. Applications have been inhibited, however, because of the need to demonstrate damage tolerance, and by cost and manufacturing risks associated with the size and complexity of the parts. The Integral Airframe Structures (IAS) Program identified a feasible integrally stiffened fuselage concept and evaluated performance and manufacturing cost compared to conventional designs. An integral skin/stiffener concept was produced both by plate hog-out and near-net extrusion. Alloys evaluated included 7050-T7451 plate, 7050-T74511 extrusion, 6013-T6511 extrusion, and 7475-T7351 plate. Mechanical properties, structural details, and joint performance were evaluated as well as repair, static compression, and two-bay crack residual strength panels. Crack turning behavior was characterized through panel tests and improved methods for predicting crack turning were developed. Manufacturing cost was evaluated using COSTRAN. A hybrid design, made from high-speed machined extruded frames that are mechanically fastened to high-speed machined plate skin/stringer panels, was identified as the most cost-effective manufacturing solution. Recurring labor and material costs of the hybrid design are up to 61 percent less than the current technology baseline.

Pettit, R. G.

Kinetics of the Cl(2)P(J)) + CH4 Reaction: Effects of Secondary Chemistry Below 300 K

Absolute rate data for the Cl(2)P(J) + CH4 yields HCl + CH3 reaction have been obtained from 218 to 298 K by using the discharge-flow resonance fluorescence technique at I Torr total pressure. The result at 298 K is (10.1 +/- 0.6) x 10(exp -14) cu cm/molecule/s. The temperature dependence in Arrhenius form is (6.5 +/- 0.9 ) x 10(exp -12) exp[(-1235 +/- 34 )/T]. The errors given are one standard deviation; overall experimental error is estimated at +/- 15%. Because of the relatively large disagreement among earlier measurements at low temperatures, the results were examined for possible effects of non-Boltzmann spin distribution and vibrational excitation of CH4, secondary chemistry of CH3 radicals, and impurities in the CH4 source. There was no significant change in the observed rate constant when an efficient spin quencher, CF4, was added and estimates indicate that vibrational partitioning in CH4 should be at the ambient reactor temperature before the start of the reaction. The results were also independent of the source of Cl atoms (microwave discharge or thermal decomposition of Cl2) and whether CH4 was purified in-situ. However, the observed rate constant did depend on initial Cl atom concentrations and to a lesser extent on CH4 concentrations. Numerical simulations were used to assess the importance of secondary chemistry over a range of reactant concentrations

Wang, J. J.

SRAM Based Re-programmable FPGA for Space Applications

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Wang, J. J.

Current Radiation Issues for Programmable Elements and Devices

State of the an programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.

Katz, R.

Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry

This report summarizes the use of SX series devices and their JTAG 1149.1 circuitry. 'JTAG' circuitry was originally designed to standardize testing of boards via a simple control port interface electrically without having to use devices such as a bed of nails tester. JTAG is also used for other functions such as executing built-in-test sequences, identifying devices, or, through custom instructions, other functions designed in by the chip designer. The JTAG circuitry is designed for test only; it has no functional use in the integrated circuit during normal operations. The JTAG circuitry and the mode of the device is controlled by a circuit block known as the 'TAP controller,' which is a sixteen-state state machine along with various registers. The controller is normally in an operational state known as TEST-LOGIC-RESET. In this state, the device is held in a fully functional, operating mode. However, a Single Event Upset (SEU) may remove the TAP controller from this state, causing a loss of control of the integrated circuit, unless certain precautions are taken, such as grounding the optional JTAG TRST signal.

Katz, Richard B.

Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry

This report summarizes the use of SX series devices and their JTAG 1149.1 circuitry. 'JTAG' circuitry was originally designed to standardize testing of boards via a simple control port interface electrically without having to use devices such as a bed of nails tester. JTAG is also used for other functions such as executing built-in-test sequences, identifying devices, or, through custom instructions, other functions designed in by the chip designer. The JTAG circuitry is designed for test only; it has no functional use in the integrated circuit during normal operations. The JTAG circuitry and the mode of the device is controlled by a circuit block known as the 'TAP controller,' which is a sixteen-state state machine along with various registers. The controller is normally in an operational state known as TEST-LOGIC-RESET. In this state, the device is held in a fully functional, operational mode. However, a Single Event Upset (SEU) may remove the TAP controller from this state, causing a loss of control of the integrated circuit, unless certain precautions are taken, such as grounding the optional JTAG TRST signal.

Katz, Richard B.

RH1020 Single Event Clock Upset Summary Report

This report summarizes the testing and analysis of "single event clock upset' in the RH1020. Also included are SEU-rate predictions and design recommendations for risk analysis and reduction. The subject of "upsets" in the RH1020 is best understood by using a model consisting of a global clock buffer and a D-type flip-flop as the basic memory unit. The RH1020 is built on the ACT 1 family architecture. As such, it has one low-skew global clock buffer with a TTL-level input threshold that is accessed via a single dedicated pin. The clock signal is driven to full CMOS levels, buffered, and sent to individual row buffers with one buffer per channel. For low-skew performance, the outputs of all of the RH1020 row buffers are shorted together via metal lines, as is done in the A1020B. All storage in the RH1020 consists of routed flip-flops, constructed with multiplexors and feedback through the routing segments. A simple latch can be constructed from a single (combinatorial or C) module; an edge-triggered flip-flop is constructed using two concatenated latches. There is no storage in the I/O modules. The front end of the clock buffering circuitry, at a common point relative to the row buffer, is a sub-circuit that was determined to be the most susceptible to heavy ions. This is due, in part, to its smaller transistors compared to the rest of the circuitry. This conclusion is also supported by SPICE simulations and an analysis of the heavy ion data, described in this report. The edge triggered D flip-flop has two single-event-upset modes. Mode one, called C-module upset, is caused by a heavy ion striking the C-module's sensitive area on the silicon and produces a soft single bit error at the output of the flip-flop. Mode two, called clock upset, is caused by a heavy ion strike on the clock buffer, generating a runt pulse interpreted as a false clock signal and consequently producing errors at the flip-flop outputs. C-module upset sensitivity in the RH1020 is essentially the same as that of its ACT 1 siblings (A1020, A1020A and A1020B), which were well tested, analyzed, and documented in the literature.

Katz, Richard B.

Current Radiation Issues for Programmable Elements and Devices

The purpose of this presentation is to discuss the COTS performance, clock upset / single event transient, device configuration upset, antifuse hardening, heavy ion SEU, total dose, proton sensitivities, latchup, and additional information and data.

Katz, Richard

Radiation Effects on Current Field Programmable Technologies

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Katz, R.

Technology and task parameters relating to the effectiveness of the bracing strategy

The bracing strategy has been proposed in various forms as a way to improve robot performance. One version of the strategy employs independent stages of motion. The first stage, referred to as the large or bracing arm, carries the second stage of motion. After the first stage has completed its motion it is braced to provide a more rigid base of motion with a more accurate relationship to the parts to be manipulated. The hypothesis is that more rapid completion of certain tasks is possible with lighter arms using the bracing strategy. While it is easy to make conceptual arguments why this should be so, it is less easy to specify even approximately when this will be true for some reasonably generic situation. There is no relevant experience base with bracing arms to be compared to non-bracing arms. Furthermore, if one were interested in obtaining such practical experience, there would be no methodical guidance on the selection of an interesting case, one in which the unproven approach, bracing, can show its superiority. If one such case exists, only the extent of applicability of the new approach is in question. One set of interesting cases is likely to be applications in which a large workspace must be covered, but where a series of small accurate moves will remain within a smaller region of the total workspace. A prototype application with these characteristics is set up and a skeleton design of arms using the competing strategies are compared.

Book, Wayne J.