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Warner, Arden [Fermilab]

Publications and source records attributed to Warner, Arden [Fermilab].

Machine-Protection System for the PIP-II Linear Accelerator: Architecture and Data Processing Schemes

PIP-II at Fermilab features a brand-new, 800 MeV leading-edge Linear Accelerator (Linac) that will enable the Fermilab complex to deliver more than a megawatt of beam power to the Long Base-line Neutrino Facility (LBNF), requiring a robust Machine Protection System (MPS) to prevent beam-induced damage to delicate cryomodules and vacuum components. Signals in various accelerator components, in both analog and digital format, are collected and processed to assest the operating conditions of the accelerator. In the situation a potential damage is foreseen, the beam permit signal will be drop. A critical element of this system is the fast Analog Machine Protection System, a high-bandwidth platform designed for real-time beam loss monitoring. The system utilizes a modular, FPGA-based architecture to digitize signals from beam-sensing devices, such as AC Current Transformers (ACCTs), non-invasive Ring Pickups (RPUs) and beam scrapers. To eliminate both high frequency as well as 60 Hz noise that might be picked up in the industrial environment, data processing schemes beyond regular digital filtering are planned and implemented.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)

Fermilab PIP-II machine protection system digitized data noise elimination scheme and its FPGA implementation

In Fermilab's PIP-II machine protection system, beam loss signals from various detectors are digitized at 125 MS/s. Noise from both high-frequency sources and low-frequency 60 Hz AC power equipment can contaminate the data. To suppress noise across these ranges—especially 60 Hz and its harmonics, which overlap with beam loss signal frequencies—advanced digital processing beyond standard filtering is required. Several real-time functional blocks were simulated and tested on an FPGA: (1) a dual time-constant discharging integrator filter, (2) a de-ripple baseline extraction and storage block, and (3) a fast-recovery discharging integrator. The nonlinear IIR integrator filter removes high-frequency noise and feeds into the baseline extractor. Upon detecting abrupt beam loss, it switches to a longer time constant to prevent baseline distortion. The de-ripple block calculates a valid baseline by averaging over multiple 60 Hz periods, storing results in a 4096-word FPGA RAM. This baseline is subtracted from raw data before integration by the fast-recovery block, which resets quickly after use. All blocks achieved expected performance and were successfully implemented on a low-cost FPGA.

Wu, Jinyuan [Fermilab]