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Wellein, Gerhard

Publications and source records attributed to Wellein, Gerhard.

Valley filtering in strain-induced α-$\mathcal{T}_3$ quantum dots

We test the valley filtering capabilities of a quantum dot inscribed by locally straining an α-$\mathcal{T}_3$ lattice. Specifically, we consider an out-of-plane Gaussian bump in the center of a four-terminal configuration and calculate the generated pseudo-magnetic field having opposite direction for electrons originating from different valleys, the resulting valley-polarized currents, and the conductance between the injector and collector situated opposite one another. Depending on the quantum dot’s width and width-to-height ratio, we detect different transport regimes with and without valley filtering for both the α-$\mathcal{T}_3$ and Dice lattice structures. In addition, we analyze the essence of the conductance resonances with high valley polarization in terms of related (pseudo) Landau levels, the spatial distribution of the local density of states and the local current densities. The observed local charge and current density patterns reflect the local inversion symmetry-breaking by the strain, besides the global inversion symmetry breaking due to the scaling parameter α. By this way we can also filter out different sublattices

36 MATERIALS SCIENCE↗

Understanding HPC Benchmark Performance on Intel Broadwell and Cascade Lake Processors

Hardware platforms in high performance computing are constantly getting more complex to handle even when considering multicore CPUs alone. Numerous features and configuration options in the hardware and the software environment that are relevant for performance are not even known to most application users or developers. Microbenchmarks, i.e., simple codes that fathom a particular aspect of the hardware, can help to shed light on such issues, but only if they are well understood and if the results can be reconciled with known facts or performance models. The insight gained from microbenchmarks may then be applied to real applications for performance analysis or optimization. In this paper we investigate two modern Intel x86 server CPU architectures in depth: Broadwell EP and Cascade Lake SP. We highlight relevant hardware configuration settings that can have a decisive impact on code performance and show how to properly measure on-chip and off-chip data transfer bandwidths. The new victim L3 cache of Cascade Lake and its advanced replacement policy receive due attention. Finally we use DGEMM, sparse matrix-vector multiplication, and the HPCG benchmark to make a connection to relevant application scenarios.

97 MATHEMATICS AND COMPUTING↗