Engineering topics

Wells, B. Earl

Publications and source records attributed to Wells, B. Earl.

7 records

NASA NTRS2004

Applying a Genetic Algorithm to Reconfigurable Hardware

This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

Wells, B. Earl↗

NASA NTRS2003

An Agent Inspired Reconfigurable Computing Implementation of a Genetic Algorithm

Many software systems have been successfully implemented using an agent paradigm which employs a number of independent entities that communicate with one another to achieve a common goal. The distributed nature of such a paradigm makes it an excellent candidate for use in high speed reconfigurable computing hardware environments such as those present in modem FPGA's. In this paper, a distributed genetic algorithm that can be applied to the agent based reconfigurable hardware model is introduced. The effectiveness of this new algorithm is evaluated by comparing the quality of the solutions found by the new algorithm with those found by traditional genetic algorithms. The performance of a reconfigurable hardware implementation of the new algorithm on an FPGA is compared to traditional single processor implementations.

Weir, John M.↗

NASA NTRS2003

Evaluation of Advanced Computing Techniques and Technologies: Reconfigurable Computing

The focus of this project was to survey the technology of reconfigurable computing determine its level of maturity and suitability for NASA applications. To better understand and assess the effectiveness of the reconfigurable design paradigm that is utilized within the HAL-15 reconfigurable computer system. This system was made available to NASA MSFC for this purpose, from Star Bridge Systems, Inc. To implement on at least one application that would benefit from the performance levels that are possible with reconfigurable hardware. It was originally proposed that experiments in fault tolerance and dynamically reconfigurability would be perform but time constraints mandated that these be pursued as future research.

Wells, B. Earl↗

NASA NTRS1998

An Analysis of an Improved Bus-Based Multiprocessor Architecture

This paper analyses the effectiveness of a hybrid multiprocessing/multicomputing architecture that is based upon a single-board-computer multiprocessor (SBCM) architecture. Based upon empirical analysis using discrete event simulations and Monte Carlo techniques, this hybrid architecture, called the enhanced single-board-computer multiprocessor (ESBCM), is shown to have improved performance and scalability characteristics over current SBCM designs.

Ricks, Kenneth G.↗

NASA NTRS1996

Applying Parallel Processing Techniques to Tether Dynamics Simulation

The focus of this research has been to determine the effectiveness of applying parallel processing techniques to a sizable real-world problem, the simulation of the dynamics associated with a tether which connects two objects in low earth orbit, and to explore the degree to which the parallelization process can be automated through the creation of new software tools. The goal has been to utilize this specific application problem as a base to develop more generally applicable techniques.

Wells, B. Earl↗

NASA NTRS1996

SEDSAT-1 Technology Development

The Students for the Exploration and Development of Space Satellite (SEDSAT-1) is an ambitious project to design, build, and fly a generally-accessible low-cost satellite which will 1) act as a technology demonstration to verify the suitability of novel optical, battery, microprocessor, and memory hardware for space flight environments, (2) to advance the understanding of tether dynamics and environmental science through the development of advanced imaging experiments, (3) to act as a communication link for radio amateurs, and (4) to provide graduate and undergraduate students with a unique multi-disciplinary experience in designing complex real-world hardware/software. This report highlights the progress made on this project during the time period from January 2, 1996 to June 1, 1996 at the end of which time the SEASIS 0.7 version software was completed and integrated on the SEASIS breadboard, a functional prototype of the Panoramic Annual Lenses (PAL) camera was developed, the preferred image compression technique was selected, the layout of the SEASIS board was begun, porting of the SCOS operating system to the command data system (CDS) board was begun, a new design for a tether release mechanism was developed, safety circuitry to inhibit tether cutting was developed and prototyped, material was prepared to support a comprehensive safety review of the project which was held at Johnson Space Center (JSC) (which was personally attended by one of the Principal Investigators), and prototype ground software was developed.

Maier, Mark W.↗

NASA NTRS1996

Development of the command data system and ground software for the SEDSAT-1 microsatellite

SEDSAT-1 is designed to be a low cost scientific satellite which is to be used to perform a minimum of five tasks which include: (1) the acquisition of a number of important parameters associated with the tethering processes from the payloads perspective (such as accelerations incurred and imaging data of the tether during deployment), (2) to act as a remote sensing platform for making measurements of the Earth's Atmosphere (allowing research to be performed in such areas as vertical lightning observation, visible light spectrography, and cloud cover studies, (3) to act as a general purpose amateur radio communication satellite relaying information back to earth, (4) to demonstrate the feasibility of the deployment in low earth orbit of advanced technology such as the Gallium Arsenide Solar Cells, Nickel Metal Hydride batteries, and multi-chip module technology and, (5) to support student's active participation in applying the disciplines of engineering and science to space-based hardware platforms. The project includes the Three-axis Accelerometer System, TAS, Experiment which is designed to report the accelerations that the satellite undergoes during the tethering operations and during the second phase of the mission when the free floating satellite comes in contact with orbit debris. The SEASIS (SEDS Earth, Atmosphere, and Space Imaging System) is another SEDSAT experiment designed to provide images of the tether during its deployment and the earth during the second phase of the mission. To control these experiments and virtually all other satellite operations the Command Data System, CDS is employed. This system utilizes a moderate complexity micro-controller controlled by tasks operating under a real-time operating system to dynamically monitor and control the satellite. The scope of this researchers efforts has been in the general area of coordinating and assisting the student researchers with the development of the CDS and ground station interfaces. This included the low level CDS hardware design and the formulization of a general software plan and schedule for both the CDS and ground station portions of the project.

Wells, B. Earl↗