Engineering topics

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)

Publications and source records attributed to Wu, Jinyuan [Fermilab] (ORCID:0000000344329521).

4 records

DOE OSTI2026

Machine-Protection System for the PIP-II Linear Accelerator: Architecture and Data Processing Schemes

PIP-II at Fermilab features a brand-new, 800 MeV leading-edge Linear Accelerator (Linac) that will enable the Fermilab complex to deliver more than a megawatt of beam power to the Long Base-line Neutrino Facility (LBNF), requiring a robust Machine Protection System (MPS) to prevent beam-induced damage to delicate cryomodules and vacuum components. Signals in various accelerator components, in both analog and digital format, are collected and processed to assest the operating conditions of the accelerator. In the situation a potential damage is foreseen, the beam permit signal will be drop. A critical element of this system is the fast Analog Machine Protection System, a high-bandwidth platform designed for real-time beam loss monitoring. The system utilizes a modular, FPGA-based architecture to digitize signals from beam-sensing devices, such as AC Current Transformers (ACCTs), non-invasive Ring Pickups (RPUs) and beam scrapers. To eliminate both high frequency as well as 60 Hz noise that might be picked up in the industrial environment, data processing schemes beyond regular digital filtering are planned and implemented.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗

DOE OSTI2026

A Complexity Agnostic Clustering Engine for Time Projection Chambers and its Implementation in FPGA

A clustering functional block implemented in field-programable-gate-array (FPGA) for time projection chambers (TPC) operating with predictable time regardless the complexity of the event is described in this paper. The clustering functional block reorganizes input data and the hits data belonging to the same clusters are output together for further process in the later stages. The clustering operation consists of two phases, data filling phase and data outputting phase, and the later uses the same number of clock cycles as the data filling phase. The clustering block can accommodate events with arbitrary number of clusters and number of hits per cluster as long as the total number of hits is within a predesigned limit. The operation time is exactly twice of the data filling time with no residual O(n2) term. The clustering block has been implemented with operating frequency of 200 MHz in a low-cost FPGA evaluation module and test results confirm the expected performance.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗

DOE OSTI2025

Fermilab PIP II Machine Protection System Digitized Data Noise Elimination Scheme and Its FPGA Implementation

In Fermilab's PIP-II machine protection system, beam loss signals from various detectors are digitized at 125 MS/s. Noise from both high-frequency sources and low-frequency 60 Hz AC power equipment can con-taminate the data. To suppress noise across these ranges especially 60 Hz and its harmonics, which overlap with beam loss signal frequencies advanced digital processing beyond standard filtering is re-quired. Several real-time functional blocks were simu-lated and tested on an FPGA: (1) a dual time-constant discharging integrator filter, (2) a de-ripple baseline extraction and storage block, and (3) a fast-recovery discharging integrator. The nonlinear IIR integrator filter removes high-frequency noise and feeds into the baseline extractor. Upon detecting abrupt beam loss, it switches to a longer time constant to prevent baseline distortion. The de-ripple block calculates a valid base-line by averaging over multiple 60 Hz periods, storing results in a 4096-word FPGA RAM. This baseline is subtracted from raw data before integration by the fast-recovery block, which resets quickly after use. All blocks achieved expected performance.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗

DOE OSTI2024

The Tiny Median Filter: A Small Size, Flexible Arbitrary Percentile Finder Scheme Suitable for FPGA Implementation

This document reports the design, implementation and testing of a small silicon resource usage, very flexible arbitrary percentile finding scheme called the Tiny Median Filter. It can be used not only as a median filter in image processing with square filtering windows, but also for applications of any percentile filter or maximum or minimum finder with any size of data set as long as the number of bits of the data is finite. It opens possibilities for image processing tasks with non-square or irregular filter windows. In this scheme, data swapping or data bit manipulating are avoided and high functional efficiency of the logic components is applied to save silicon resources. Some logic functions are absorbed into other functions to further reduce the complexity. The combinational logic paths are designed to be sufficiently short so that the firmware can be compiled to the maximum operating frequency allowed by the block memories of the FPGA devices. The Tiny Median Filter receives, processes and output data in non-stop manner with no irregular timing which helps to simplify design of surrounding stages.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗