A framework for integrating genomics, microbial traits, and ecosystem biogeochemistry
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59 BASIC BIOLOGICAL SCIENCES↗
Engineering topics
Wu, Qiong
Publications and source records attributed to Wu, Qiong.
Structure and tunable temperature coefficient of magnetization of Mn 4-x Ga x C alloys prepared by induction melting method
The magnetization of most magnetic materials decreases monotonically with increasing temperature. In this work, we found that the temperature coefficient of magnetization of Mn 4-x Ga x C alloys can be tuned from negative values to positive values by controlling the composition x. The antiperovskite type Mn 4-x Ga x C (0.05 ≤ x ≤ 0.75) alloys were prepared by using induction melting method, which is more efficient in large-scale production and obtaining full-density alloys in comparison with the traditional solid-state-reaction method. The values of the temperature coefficient of magnetization of Mn 4-x Ga x C change continuously from negative to positive with decreasing x. The Mn 4-x Ga x C alloys with highly thermal-stable magnetization is expected to present in the composition range of 0.15 < x < 0.25. The saturation magnetization of Mn 4-x Ga x C increases with increasing x, owing to the reduced number of antiferromagnetically coupled Mn atoms at the cubic corner with the face centered Mn atoms. Most Mn 4-x Ga x C alloys with varying x display near-zero remanent magnetization and coercivity at room temperature. The Currie temperature of Mn 4-x Ga x C decreases with increasing x. The x-ray photoelectron spectra of Mn 2p, Ga 2p, and C 1 s reveal distinct splitting due to the diverse chemical states of these atoms at different lattice positions and/or phases. Our work has developed a class of alloys capable of offering a desired temperature coefficient of magnetization across a broad temperature range, thereby offering a method to manipulate the thermodynamics of magnetization.
Magnetic properties↗
The EIC accelerator: design highlights and project status
The design of the electron-ion collider (EIC) at Brookhaven National Laboratory is well underway, aiming at a peak electron-proton luminosity of 10e+34 cm^-1·sec^-1. This high luminosity, the wide center-of-mass energy range from 29 to 141 GeV (e-p) and the high level of polarization require innovative solutions to maximize the performance of the machine, which makes the EIC one of the most challenging accelerator projects to date. The complexity of the EIC will be discussed, and the project status and plans will be presented.
43 PARTICLE ACCELERATORS↗
Progress on the design of the interaction region of the Electron-Ion Collider EIC
We present an update on the design of the Interaction Region (IR) for the the Electron Ion Collider (EIC) being built at Brookhaven National Laboratory (BNL). The EIC will collide high energy and highly polarized hadron and electron beams with a center of mass energy up to 140 GeV with luminosities of up to 10^34 /cm^2/s. The IR, located at RHIC's IR6, is designed to meet the requirements of the nuclear physics community as outlined in [1]. A second IR is technically feasible but not part of the project.The magnet apertures are sufficiently large to allow desired collision products to reach the far-forward detectors; the electron magnet apertures in the rear direction are chosen to be large enough to pass the synchrotron radiation fan. In the forward direction the electron apertures are large enough for non-Gaussian tails.The paper discusses a number of recent recent changes to the design. The machine free region was recently increased from 9 to 9.5 m to allow for more space in the forward direction for the detector. The superconducting magnets on the forward side now operate at 1.9 K, which helps crosstalk and space issues.
43 PARTICLE ACCELERATORS↗
ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library
PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.
Schuler, Robert L., Jr.↗
All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library
PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.
Shuler, Robert L., Jr.↗