Speed enhancement with soft computing hardware
We will review our work on electronic neural networks and evolvable hardware to bring out speed advantage.
Engineering topics
Publications and source records attributed to Zebulum, R..
We will review our work on electronic neural networks and evolvable hardware to bring out speed advantage.
In this paper we describe the hardware evolution of analog circuits performing signal separation tasks using JPL's Stand-Alone Board-Level Evolvable System (SABLES).
This paper introduces a new approach to the development of equivalent models. Models of various accuracy and simulation speed may be needed in different contexts of design and analysis, or within different simulators.
We describe in this paper the rationale and design of an evovlable hardware platform based on the use of a stand-alone processor and a Field Programable Transistor Array.
This paper introduces the concept of polymorphic electronics (polytronics) - referring to electronics with superimposed built-in functionality.
This paper introduces the concept of polymorphic electronics (polytronics)- referring to electronics with superimposed built-in functionality.
In this paper we describe the initial development of efficient mechanisms for smart sensing which will lead to higher quality data.
This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in-situ circuit redesign/reconfiguration during operation in extreme environments.
This paper presents JPL progress in building evolution-oriented reconfigurable devices.
Temperature tolerant electronics and long life survivability are key capabilities required for future NASA/JPL missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques, e.g., as offered by bias cancellation circuits, have also been employed. This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in situ circuit redesign/reconfiguration during the operation in the environment. This technology would complement material/device advancements and bring closer the success of missions in harsh environments. Additional information is contained in the original extended abstract.
This paper discusses the use of Evolvable Hardware (EHW) in automatic synthesis of electronic circuits for computational intelligence (CI) hardware.
This paper discusses the use of Evolvable Hardware (EHW) in automatic synthesis of electronic circuits for computational intelligence (CI) hardware.
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Explore the source record for details and available documents.
For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.
This paper describes the EHW development system, a tool that performs the evolutionary synthesis of electronic circuits, using the SPICE simulator and the Field Programmable Transistor Array hardware (FPTA) developed at JPL.
The paper presents and compares two approaches to design fault-tolerant evolvable hardware: one based on the fitness definition and the other based on the population statistics.
In this paper we describe the initial development of efficient mechanisms for smart on-board adaptive sensing, adaptively controlling the reconfigurable pre-processing analog electronics using evolvable hardware, which will lead to higher quality, lean data.