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Zhang, Yuhao

Publications and source records attributed to Zhang, Yuhao.

8 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Vertical GaN Superjunction Diode on Sapphire with Kilovolt Dynamic Breakdown Voltage

The development of superjunction structures for use in vertical wide bandgap power devices promise to break the 1-D material limits. Additionally, the possibility of utilizing heteroepitaxial GaN-on-Sapphire wafer for vertical devices can significantly trim the material and device cost. This work introduces a quasi-vertical GaN-on-Sapphire superjunction PN diode design utilizing sputtered p-NiO on the etched GaN fins for superjunction formation. DC breakdown voltage is shown to vary with superjunction charge imbalance and significantly exceed the expected 1-D planar limit of 350V given the epilayer design used. A maximum breakdown voltage of 840 V is extracted for near charge balance conditions limited by leakage current. Dynamic breakdown of the device is characterized as a function of reverse voltage slew rate. A maximum dynamic breakdown voltage of 1160 V under a reverse voltage slew rate of 2000 V/μs is found.

Porter, Matthew↗
DOE OSTI2024

Output Capacitance Loss of GaN HEMTs in Steady-State Switching

The output capacitance (C OSS ) loss, a loss produced when the device’s output capacitor is charged and discharged, has become a concern for GaN high electron mobility transistors (HEMTs) in high-frequency applications. This work presents a new, easy-to-implement method for the C OSS loss characterization based on the unclamped inductive switching (UIS) setup. As compared to prior approaches, this method involves the device’s ON-state conduction and could measure the C OSS loss in a single pulse and the steady-state switching. The C OSS loss of three types of mainstream commercial GaN HEMTs is characterized, which exhibit some common dependencies including a non-monotonic relation with the dv/dt (or resonance frequency), a linear relation with the ON-state current, a power-law relation with the peak blocking voltage, and little temperature dependence. In addition, their C OSS losses all show minimal distinctions in a single pulse and the steady-state switching, despite the increased on-resistance in the steady-state switching. Furthermore, this suggests that the traps accounting for the C OSS loss possess different de-trapping time constants as compared to the traps governing the dynamic on-resistance. Finally, a unified model is established to describe the C OSS loss of all three types of GaN HEMTs. These results provide important references for the high-frequency application of GaN HEMTs and new insights into the physical origin of their C OSS loss.1

42 ENGINEERING↗
DOE OSTI2023

2 kV, 0.7 mΩ•cm2 Vertical Ga2O3 Superjunction Schottky Rectifier with Dynamic Robustness

We report the first experimental demonstration of a vertical superjunction device in ultra-wide bandgap (UWBG) Ga 2 O 3 . The device features 1.8 μm wide, 2×10 17 cm -3 doped n-Ga 2 O 3 pillars wrapped by the charge-balanced p-type nickel oxide (NiO). The sidewall NiO is sputtered through a novel self-align process. Benefited from the high doping in Ga 2 O 3 , the superjunction Schottky barrier diode (SJ-SBD) achieves a ultra-low specific on-resistance (R ON,SP ) of 0.7 mΩ•cm 2 with a low turn-on voltage of 1 V and high breakdown voltage (BV) of 2000 V. The R ON,SP ~BV trade-off is among the best in all WBG and UWBG power SBDs. The device also shows good thermal stability with BV > 1.8 kV at 175 °C. In the unclamped inductive switching tests, the device shows a dynamic BV of 2.2 kV and no degradation under 1.7 kV repetitive switching, verifying the fast acceptor depletion in NiO under dynamic switching. Such high-temperature and switching robustness are reported for the first time in a heterogeneous superjunction. These results show the great potential of UWBG superjunction power devices.

Qin, Yuan↗
DOE OSTI2023

1 kV Self-Aligned Vertical GaN Superjunction Diode

This work demonstrates vertical GaN superjunction (SJ) diodes fabricated via a novel self-aligned process. The SJ comprises n-GaN pillars wrapped by the charge-balanced p-type nickel oxide (NiO). After the NiO sputtering around GaN pillars, the self-aligned process exposes the top pillar surfaces without the need for additional lithography or a patterned NiO etching which is usually difficult. The GaN SJ diode shows a breakdown voltage (B V) of 1100 V, a specific on-resistance (R ON ) of 0.4 mΩ· cm2, and a SJ drift-region resistance ( R dr ) of 0.13 mΩ· cm2. Further, the device also exhibits good thermal stability with B V retained over 1 kV and R ON dropped to 0.3 mΩ· cm2 at 125°C. The trade-off between B V and R dr is superior to the 1D GaN limit. These results show the promise of vertical GaN SJ power devices. The self-aligned process is applicable for fabricating the heterogeneous SJ based on various wide- and ultra-wide bandgap semiconductors.

42 ENGINEERING↗
DOE OSTI2023

Implanted Guard Ring Edge Termination With Avalanche Capability for Vertical GaN Devices

Edge termination is the key building block in power devices to enable near-ideal, avalanche breakdown voltage (BV). Here, this work presents the design, fabrication, and physics of a GaN guard ring (GR) edge termination formed by selective-area nitrogen implantation through an epitaxial p-GaN layer. The fabrication of this termination only includes a single implantation step that does not require precise control of implant depth, rendering a large process latitude. The selective-area implantation produces p-GaN rings that are separated by the implanted, semi-insulating regions. The number and spacing of the p-type rings are found to determine the BV of the vertical GaN p-n diode. The 16-ring structure enables a BV of 1800 V, being 88% of the theoretical 1-D parallel-plane limit. Avalanche characteristics are observed in devices with a large variety of GR designs. Finally, we present a comprehensive survey on the efficiency, fabrication complexity, real estate, and avalanche capability of various edge termination techniques that have been reported in vertical GaN devices. The high efficiency (among the highest reported in avalanche-capable GaN terminations), simple and robust fabrication process, and uniform avalanche capability make this implanted GR a promising edge termination for high-voltage GaN devices.

42 ENGINEERING↗
DOE OSTI2023

Origin of Soft-Switching Output Capacitance Loss in Cascode GaN HEMTs at High Frequencies

Output capacitance (C OSS ) loss (E DISS ) is produced when the C OSS of a power device is charged and discharged, which ideally should be a lossless process. This loss was recently revealed to be a crucial concern for GaN high electron mobility transistors (HEMTs) in high-frequency soft-switching applications. Among various GaN devices, the composite-type, cascode GaN HEMT was reported to show the largest E DISS with a voltage dependence distinct from discrete GaN HEMTs. However, the physical origins of the EDISS in cascode GaN HEMTs remain unclear. This work fills this gap by identifying three loss components and, for the first time, experimentally quantifying them in the multi-MHz resonant switching. These loss components include a) the avalanche loss of Si MOSFET, b) the intrinsic E DISS of GaN HEMT, and c) the Si avalanche-induced GaN turn-ON loss. The last component was found to dominate E DISS at high voltage. By eliminating the Si avalanche and the associated loss components (a) and (c), the E DISS of cascode GaN HEMTs can be reduced by up to 75% at the price of an increase in output charge and switching transition time. Furthermore, these results provide new physical insights and practical guidelines to trim the soft-switching loss of cascode GaN HEMTs in high-frequency applications.

42 ENGINEERING↗
DOE OSTI2023

1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier

Here, this work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plane junction electric field of 2.8 MV/cm. The device also shows low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 mΩ∙ cm 2 . Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.

42 ENGINEERING↗