NASA NTRS · 19720000642
Redundancy approaches in bubble domain memories
Abstract
Fabrication of integrated circuit chips to compensate for faulty memory elements is discussed. Procedure for testing chips to determine extent of redundancy and faults is described. Mathematical model to define operation is presented. Schematic circuit diagram of test equipment is provided.
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Almasi, G. S., Schuster, S. E.. 1972-10-01. Redundancy approaches in bubble domain memories. https://ntrs.nasa.gov/citations/19720000642
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