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NASA NTRS ยท 19730000479

Input-output, expandable-parity network

Abstract

Large-scale integrated circuit generates and checks parity of four eight-bit registers. In addition, circuit will indicate by output signal whether parity error exists. Circuit can also generate or check parity of words up to 32 bits. This is done by making appropriate internal wiring connections on the large-scale integrated chip.

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BibTeXRIS

Mckevitt, J. F., III. 1974-03-01. Input-output, expandable-parity network. https://ntrs.nasa.gov/citations/19730000479

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