NASA NTRS · 19740052027
Response of an all digital phase-locked loop
Abstract
An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of threshold extension. This substantiates results obtained for analog PLL's.
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Garodnick, J., Greco, J., Schilling, D. L.. 1974-06-01. Response of an all digital phase-locked loop. https://ntrs.nasa.gov/citations/19740052027
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