Phase-locked loops

Abstract

The basic analysis and design procedures are described for the realization of analog phase-locked loops (APLL), hybrid phase-locked loops (HPLL), discrete phase-locked loops, and digital phase-locked loops (DPLL). Basic configurations are diagrammed, and performance curves are given. A discrete communications model is derived and developed. The use of the APLL as an optimum angle demodulator and the Kalman-Bucy approach to APLL design are discussed. The literature in the area of phase-locked loops is reviewed, and an extensive bibliography is given. Although the design of APLLs is fairly well documented, work on discrete, hybrid, and digital PLLs is scattered, and more will have to be done in the future to pinpoint the formal design of DPLLs.