NASA NTRS · 19750013449
Design, processing, and testing of LSI arrays for space station
Abstract
Data for the beam-leaded silicon-on-sapphire (SOS) process using the TA5388 dual-complementary pair plus inverted circuit show the stability of the dc device characteristics through the complete beam-lead processing and packaging steps. A more complex circuit, the TA6567 - a silicon-gate, voltage-sense BL/CMOS/SOS 256-bit RAM, has also been made that was functionally perfect at wafer probe. Efforts to increase the yield of this circuit and to obtain electrically perfect packaged units are discussed.
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Schneider, W. C.. 1975-03-01. Design, processing, and testing of LSI arrays for space station. https://ntrs.nasa.gov/citations/19750013449
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