NASA NTRS · 19800000004
Independent synchronizer for digital decoders
Abstract
Logic circuit synchronizes branches of any convolution code-decoder at low signal to noise ratios. Parity checks determine correct node synchronization. Device maintains synchrony as low as -3 dB. Circuit consists of 15 stage shift register, three up down counters, and some logic gates.
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Stiffler, J. J.. 1980-08-01. Independent synchronizer for digital decoders. https://ntrs.nasa.gov/citations/19800000004
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