NASA NTRS · 19810003814
User's manual for large-scale integrated circuit layout check program
Abstract
A computer program is described that checks for the correctness of chip design layout generated by the Banning Placement Routing Folding program (PRF) by verifying agreement between a specified circuit design and a corresponding computer generated circuit layout as stored on the Artwork (PRF output) tape. An example computer run is included.
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1978-09-01. User's manual for large-scale integrated circuit layout check program. https://ntrs.nasa.gov/citations/19810003814
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