NASA NTRS · 19820022029
Chip level simulation of fault tolerant computers
Abstract
Chip-level modeling techniques in the evaluation of fault tolerant systems were researched. A fault tolerant computer was modeled. An efficient approach to functional fault simulation was developed. Simulation software was also developed.
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Armstrong, J. R.. 1982-05-31. Chip level simulation of fault tolerant computers. https://ntrs.nasa.gov/citations/19820022029
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