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NASA NTRS ยท 19830000255

Error-Compensated Integrate and Hold

Abstract

Differencing circuit cancels error caused by switching transistors capacitance. In integrate and hold circuit using JFET switch, gate-to-source capacitance causes error in output voltage. Differential connection cancels out error. Applications in systems where very low voltages sampled or many integrate-and -hold cycles before circuit is reset.

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BibTeXRIS

Matlin, M.. 1984-04-01. Error-Compensated Integrate and Hold. https://ntrs.nasa.gov/citations/19830000255

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