NASA NTRS · 19830026325
Chip level simulation of fault tolerant computers
Abstract
Chip level modeling techniques, functional fault simulation, simulation software development, a more efficient, high level version of GSP, and a parallel architecture for functional simulation are discussed.
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Armstrong, J. R.. 1983-01-01. Chip level simulation of fault tolerant computers. https://ntrs.nasa.gov/citations/19830026325
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