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NASA NTRS · 19830030684

A fast microprocessor communication network design for interprocessor communications for an integrated flight control system

Abstract

A node design with connectivity four is presented whose communication processor handles data at four million bits/sec on each of the four channels into the node, and on each of the four channels out of the node, for a total node capacity of 32 million bits/sec. An integrated flight control system real-time application of this communication network design is discussed. It is shown that such high speed node communication hardware, arranged in the topological configuration of a minimum diameter graph with connectivity four and all links active, has good potential for real time control applications requiring reliability, availability, and survivability characteristics.

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BibTeXRIS

Kelly, G. L., Jiang, P.-W.. 1982-01-01. A fast microprocessor communication network design for interprocessor communications for an integrated flight control system. https://ntrs.nasa.gov/citations/19830030684

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