Test chip assembler and test program generator

Abstract

One of the major problems in working at the geometry level for the generation of either test structure or functional circuit designs is the amount of labor involved in the design phase. To reduce the amount of labor involved in both the design and test of the structures used, JPL has developed a design and test program consisting of a Test Chip Assembler (TCA) and a Test Program Generator (TPG), which creates the geometrical description of the structures and generates the necessary test information using a high-level language. This system reduces the design time for a test chip by a factor of 30. To analyze the data obtained from wafer probing, a statistical package called STMJPL was developed. Some of the capabilities of the JPL software (STMJPL) are described.