Real-time data compressor for Eos-class missions

Abstract

A conceptual design for a real-time VLSI compressor capable of processing rate up to one gigabit per second is presented. This scheme is capable of providing a three-to-one distortion-free data reduction factor to both the High Resolution Imaging Spectrometer and processed SAR imaging data. The design uses a VLSI parallel/piplined architecture capable of processing at a real time rate. The design consists of a parallel array of VLSI compressor modules. Each module is built on a single customized VLSI chip using existing state-of-the-art semiconductor technology.