Transputer finite element solver

Abstract

In January 1987, SPARTA received a Phase I SBIR award from the NASA Lewis Research Center to investigate the feasibility of a finite element solver implemented on multiple VLSI processors. The transputer was chosen as the processor for the feasibility study since it combined low cost with high performance and was specifically designed to directly link with other transputers to form networks of multiple processors. A brief description of transputers, a summary of the SBIR feasibility study, and a discussion of issues concerning a large scale transputer based finite element solver (TBFES) and the performance levels which can be expected are discussed.