NASA NTRS · 19900041833
Single chip fixed frequency bit synchronizer
Abstract
A single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device is described. The bit synchronizer is modeled after a digital transition tracking loop for symbol estimation and employs a first-order incremental phase modulator for closed-loop symbol synchronization. The BER and tracking performance is modeled and compared to optimum designs. The bit synchronizer was developed for the Space Shuttle.
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Butler, Madeline J., James, Calvin L.. 1989-01-01. Single chip fixed frequency bit synchronizer. https://ntrs.nasa.gov/citations/19900041833
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