Synchronous demodulator

Abstract

A synchronous demodulator includes a switch which is operated in synchronism with an incoming periodic signal and both divides and applies that signal to two signal channels. The two channels each include a network for computing and holding, for a predetermined length of time, the average signal value on that channel and applies those valves, in the form of two other signals, to the inputs of a differential amplifier. The networks may be R-C networks. The output of the differential amplifier may or may not form the output of the synchronous detector and may or may not be filtered. The output will not include a periodic signal due to the presence of a dc offset. Additionally, the output will not contain any substantial ripple due to periodic components in the input signal. In a somewhat more complex version, containing twice the structural components of the above synchronous demodulator with a more complex switching mechanism, essentially all ripple due to periodic components in the input signal are eliminated.