NASA NTRS · 19910056166
Box schemes and their implementation on the iPSC/860
Abstract
Research on algoriths for efficiently solving fluid flow problems on massively parallel computers is continued in the present paper. Attention is given to the implementation of a box scheme on the iPSC/860, a massively parallel computer with a peak speed of 10 Gflops and a memory of 128 Mwords. A domain decomposition approach to parallelism is used.
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Chattot, J. J., Merriam, M. L.. 1991-01-01. Box schemes and their implementation on the iPSC/860. https://ntrs.nasa.gov/citations/19910056166
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