Compensated digital readout family

Abstract

ISC has completed test on an IC which has 32 channels of amplifiers, low pass anti-aliasing filters, 13-bit analog-to-digital (A/D) converters with non-uniformity correction per channel and a digital multiplexer. The single slope class of A/D conversion is described, as are the unique variations required for incorporation of this technique for use with on-focal plane detector readout electronics. This paper describes the architecture used to implement the digital on-focal plane signal processing functions. Results from measured data on a test IC are presented for a circuit containing these functions operating at a sensor frame rate of 1000 hertz.