Implementation and performance of the Magellan digital correlator subsystem

Abstract

The Magellan synthetic aperture radar (SAR) produces Venus surface images from data collected by the SAR carried on board the Magellan spacecraft. The core of the primary Magellan SAR processor is the digital correlator subsystem (DCS). The pipeline DSC architecture enables the Magellan primary SAR processor (PSP) to achieve real-time data processing capability. The implementation and performance of the DSC are described. Hardware (H/W) constraints that influenced the processing algorithm design are highlighted.