NASA NTRS · 19940004375
High performance pipelined multiplier with fast carry-save adder
Abstract
A high-performance pipelined multiplier is described. Its high performance results from the fast carry-save adder basic cell which has a simple structure and is suitable for the Gate Forest semi-custom environment. The carry-save adder computes the sum and carry within two gate delay. Results show that the proposed adder can operate at 200 MHz for a 2-micron CMOS process; better performance is expected in a Gate Forest realization.
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Wu, Angus. 1990-11-06. High performance pipelined multiplier with fast carry-save adder. https://ntrs.nasa.gov/citations/19940004375
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