NASA NTRS · 19940016614
Test results for SEU and SEL immune memory circuits
Abstract
Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.
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Wiseman, D., Canaris, J., Whitaker, S., Gambles, J., Arave, K., Arave, L.. 1993-01-01. Test results for SEU and SEL immune memory circuits. https://ntrs.nasa.gov/citations/19940016614
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