NASA NTRS · 19950017962
An optimized implementation of a fault-tolerant clock synchronization circuit
Abstract
A fault-tolerant clock synchronization circuit was designed and tested. A comparison to a previous design and the procedure followed to achieve the current optimization are included. The report also includes a description of the system and the results of tests performed to study the synchronization and fault-tolerant characteristics of the implementation.
Keep this discovery
Explore connections, maps & timelines
Torres-Pomales, Wilfredo. 1995-02-01. An optimized implementation of a fault-tolerant clock synchronization circuit. https://ntrs.nasa.gov/citations/19950017962
Cite the original work for its findings. Save a collection to share your selection of sources.