NASA NTRS · 19970001359
CMOS VLSI Layout and Verification of a SIMD Computer
Abstract
A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.
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Zheng, Jianqing. 1996-05-12. CMOS VLSI Layout and Verification of a SIMD Computer. https://ntrs.nasa.gov/citations/19970001359
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