NASA NTRS · 20090043053
Universal programmable logic gate and routing method
Abstract
An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
Keep this discovery
Explore connections, maps & timelines
Fijany, Amir, Vatan, Farrokh, Akarvardar, Kerem, Blalock, Benjamin, Chen, Suheng, Cristoloveanu, Sorin, Kolawa, Elzbieta, Mojarradi, Mohammad M., Toomarian, Nikzad. 2009-04-07. Universal programmable logic gate and routing method. https://ntrs.nasa.gov/citations/20090043053
Cite the original work for its findings. Save a collection to share your selection of sources.