NASA NTRS · 20110015395
Four-gate transistor analog multiplier circuit
Abstract
A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.
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Mojarradi, Mohammad M., Blalock, Benjamin, Cristoloveanu, Sorin, Chen, Suheng, Akarvardar, Kerem. 2011-08-30. Four-gate transistor analog multiplier circuit. https://ntrs.nasa.gov/citations/20110015395
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