Search NASA⌕ Search
Home/Archive/NASA NTRS

NASA NTRS · 20210001527

A Systematic Approach to Hardware Qualification

Cornford, Steven L.·Barela, Phillip R.
View original source ↗Export metadata ↓

Abstract

A systematic approach for the development of a hardware qualification approach is described. This approach stems from the need to break the "Catch-22" of not being able to fly new technology because it hasn't flown. A physics of failure approach is used to identify failure modes and the impact and likelihood of these failures on the mission requirements is plotted in a Requirements Matrix. These same failure modes are plotted against the effectiveness of the available Preventions, Analyses, Control and Tests (PACTs) at screening for, or eliminating, these failure modes in a Test Effectiveness Matrix. Matrix multiplication results in a ranked set of PACTs which can be sorted according to cost and redundancy with other PACTs. This, and other information which results from the process, will allow project managers to make more informed decisions regarding the cost and risk tradeoffs inherent in any qualification program.

Explore related subjects

hardwarequalification

Keep this discovery

Explore connections, maps & timelines

BibTeXRIS

Cornford, Steven L., Barela, Phillip R.. 1995-05-02. A Systematic Approach to Hardware Qualification. https://ntrs.nasa.gov/citations/20210001527

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related reports

DOE OSTI2020

On the Computational Viability of Quantum Optimization for PMU Placement

Using optimal phasor measurement unit placement as a prototypical problem, we assess the computational viability of the current generation D-Wave Systems 2000Q quantum annealer for power systems design problems. We reformulate minimum dominating set for the annealer hardware, solve the reformulation for a standard set of IEEE test systems, and benchmark solution quality and time to solution against the CPLEX optimizer and simulated annealing. For some problem instances the 2000Q outpaces CPLEX. For instances where the 2000Q underperforms with respect to CPLEX and simulated annealing, we suggest hardware improvements for the next generation of quantum annealers.

hardware↗
NASA NTRS2013

Low-Cost Space Hardware and Software

The goal of this project is to demonstrate and support the overall vision of NASA's Rocket University (RocketU) through the design of an electrical power system (EPS) monitor for implementation on RUBICS (Rocket University Broad Initiatives CubeSat), through the support for the CHREC (Center for High-Performance Reconfigurable Computing) Space Processor, and through FPGA (Field Programmable Gate Array) design. RocketU will continue to provide low-cost innovations even with continuous cuts to the budget.

hardware↗