Exploring formal verification methodology for FPGA-based digital systems

Abstract

With the Life Extension Programs (LEPs), many nuclear weapon (NW) analog electronic components are being replaced by modern digital devices, increasing system complexities dramatically. Ensuring the reliability, security, and robustness of these upgraded systems is critically important. Many custom hardware systems throughout the NW operations space rely on Field-Programmable Gate Arrays (FPGAs) to implement sophisticated logic. Effective verification, while increasing confidence, can reduce the overall effort in system debugging and testing.