DOE OSTI · 1093240
Low delay and area efficient soft error correction in arbitration logic
Abstract
There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.
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Sugawara, Yutaka. 2013-09-10. Low delay and area efficient soft error correction in arbitration logic. https://www.osti.gov/biblio/1093240
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